The present invention relates to an active matrix substrate and a method of making the substrate and also relates to a display device including the active matrix substrate and a method for fabricating the display device.
Recently, liquid crystal display devices (LCDs) have been further broadening their applications. LCDs were normally used indoors as image display devices for desktop computers or TV, sets. But now LCDs are often used as video or information display devices for various types of mobile electronic units including cell phones, notebook or laptop computers, portable TV sets, digital cameras and digital camcorders and for car-mounted electronic units like a car navigation system.
Some types of LCDs are addressed using matrix electrodes. Those matrix-addressed LCDs are roughly classifiable into the two categories of passive- and active-matrix-addressed LCDs. In an active-matrix-addressed LCD, pixels are arranged in columns and rows as its name signifies, and each of those pixels is provided with a switching element. And by controlling those switching elements using data and gate lines that are arranged to cross each other, the LCD of this type can supply desired signal charge (i.e., data signal) to a selected one of the pixel electrodes.
Hereinafter, a known active-matrix-addressed LCD will be described with reference to FIGS. 43 and 44. FIG. 43 illustrates a schematic configuration for a known LCD of that type. FIG. 44 illustrates a cross-sectional structure for a typical liquid crystal panel.
As shown in FIG. 43, the LCD includes liquid crystal panel 50 and gate and source drive circuits 51 and 52 with gate and source drivers 53. The panel 50 spatially modulates incoming light. The gate drive circuit 51 selectively drives switching elements in the liquid crystal panel 50, while the source drive circuit 52 supplies a signal to each pixel electrode in the panel 50.
As shown in FIG. 44, the panel 50 includes: a pair of transparent insulating substrates 54 and 55 of glass; a liquid crystal layer 38 interposed between the substrates 54 and 55; and a pair of polarizers 56 placed on the outer surfaces of the substrates 54 and 55. The liquid crystal layer 38 may be a twisted nematic liquid crystal layer, for example.
On the inner surface of the substrate 54 facing the liquid crystal layer 38, pixel electrodes 114 are arranged in matrix. A common transparent electrode 36 is formed on the inner surface of the substrate 55. In this construction, a desired voltage can be applied to a selected part of the liquid crystal layer 38 using the pixel electrodes 114 and common transparent electrode 36. Each of the pixel electrodes 14 is connected to the source drive circuit 52 by way of its associated thin-film transistor (TFT) 110 and data line (not shown in FIG. 44). As shown in FIG. 44, the TFTs 110 are formed on the substrate 54. The switching operation of the TFTs 110 is controllable using gate lines (not shown in FIG. 44, either), which are connected to the gate drive circuit 51 and formed on the substrate 54.
On the inner surface of the substrate 55 facing the liquid crystal layer 38, black matrix 35, R, G and B color filters and common transparent electrode 36 have been formed.
The inner surface of the substrates 54 and 55 facing the liquid crystal layer 38 is covered with an alignment film 37. And in the liquid crystal layer 38, spacers 40 with a size of several μm are dispersed.
The substrate 54 including these members thereon is collectively called an “active matrix substrate”, while the substrate 55 with those members thereon is called a “counter substrate”.
Hereinafter, various structures for known active matrix substrates will be described.
FIG. 45A illustrates a layout for a unit pixel region defined for a known active matrix substrate, while FIG. 45B illustrates a cross section of the unit pixel region taken along the line A-A′ shown in FIG. 45A.
In the example illustrated in FIGS. 45A and 45B, multiple gate lines 102 and multiple data lines 105 are formed over a glass substrate 121 so as to cross each other. More specifically, the gate lines 102 belong to a first layer on the glass substrate 121, while the data lines 105 belong to a second layer located over the first layer. And the gate and data lines 102 and 105 are electrically isolated from each other by an insulating film 104 belonging to a third intermediate layer between the first and second layers.
In each rectangular region surrounded by the gate and data lines 102 and 105, a pixel electrode 114 has been formed by patterning a transparent conductive film, for example. The pixel electrode 114 receives signal charges from associated one of the data lines 105 by way of a TFT 110 that has been formed near the intersection between the associated data line 105 and one of the gate lines 102. A storage capacitance line 113 has been formed under the pixel electrode 114 to extend parallel to the gate lines 102. Accordingly, a storage capacitance is created between the pixel electrode 114 and storage capacitance line 113.
As shown in FIG. 45B, the TFT 110 includes gate electrode 103, gate insulating film 104, intrinsic (i-) semiconductor layer 106, doped semiconductor layer 107 and source/drain electrodes 108 and 109. The gate electrode 103 is a branch extended vertically from the gate line 102 as shown in FIG. 45A. The gate electrode 103 is covered with the gate insulating film 104. The semiconductor layer 106 is located right over the gate electrode 103 with the gate insulating film 104 interposed therebetween. The doped semiconductor layer 107 exists on the i-semiconductor layer 106. And the source/drain electrodes 108 and 109 are electrically connected to source/drain regions defined in the i-semiconductor layer 106 by way of the doped semiconductor layer 107. As shown in FIG. 45A, the source electrode 108 is a branch extended vertically from the data line 105 and forms part of the data line 105.
The drain electrode 109 is a conductive member that electrically connects the drain region of the TFT 110 and the pixel electrode 114 together. The drain electrode 109, as well as the data lines 105 and source electrode 108, is formed by patterning a metal film. That is to say, in the illustrated example, the data lines 105 and source/drain electrodes 108 and 109 belong to the same layer, and their layout is determined by a mask pattern for use in a photolithographic process.
The source/drain electrodes 108 and 109 are connected together via a channel region defined in the i-semiconductor layer 106. And the electrical continuity of the channel region is controllable by the potential level at the gate electrode 103. Where the TFT 110 is of n-channel type, the TFT 110 can be turned ON by raising the potential level at the gate electrode 103 to the inversion threshold voltage of the transistor 110 or more. Then, the source/drain electrodes 108 and 109 are electrically continuous to each other, thereby allowing charges to be exchanged between the data line 105 and pixel electrode 114.
To operate the TFT 110 properly, at least part of the source/drain electrodes 108 and 109 should overlap with the gate electrode 103. Normally, the gate electrode 103 has a line width of about 10 μm or less. Accordingly, in a photolithographic process for forming the data lines 105 and source/drain electrodes 108 and 109, these members 105, 108 and 109 should be aligned accurately enough with the gate electrode 103 already existing on the substrate 121. Normally, an alignment accuracy required is on the order of ±several micrometers or even less.
Also, the size of the area where the gate and drain electrodes 103 and 109 overlap with each other defines a gate-drain capacitance Cgd, which is one of key parameters determining the resultant display performance. That is to say, if the gate-drain capacitance Cgd values are not distributed uniformly enough within the substrate plane, then the display quality will deteriorate noticeably. For that reason, the alignment accuracy of an exposure system is controlled at ±1 μm or less in an actual manufacturing process to minimize the misalignment.
As can be seen, extremely high alignment accuracy is recently required in making active matrix substrates. To meet that heavy demand, high-precision exposure systems have been developed and actually operated. Before those high-alignment-accuracy exposure systems were available, however, a layout for an active matrix substrate used to be modified in some way or other to increase the alignment margin as much as possible and thereby raise the production yield.
FIG. 46A illustrates a layout that was proposed for an active matrix substrate when exposure systems still had low alignment accuracy. In the arrangement shown in FIG. 46A, the drain electrode 109 of a TFT 110 extends from a pixel electrode 114 parallel to a data line 105 and crosses a gate line 102. The TFT 110 is formed at and around the intersection between the data and gate lines 105 and 102. In the example illustrated in FIGS. 46A and 46B, the gate and data lines 102 and 105 have no branches, the gate line 102 itself serves as a gate electrode and part of the data line 105 serves as a source electrode 108.
An active matrix substrate with this structure is made in the following manner.
First, transparent conductive film 161 and doped semiconductor layer 107 are deposited in this order over a glass substrate 101, and then patterned using a first mask, thereby forming data lines 105, drain electrodes 109 and pixel electrodes 114.
Next, i-semiconductor layer 106, gate insulating film 104 and metal thin film 102 are deposited in this order over the structure prepared in the previous process step. Then, the metal thin film 102, gate insulating film 104 and i-semiconductor layer 106 are sequentially patterned using a second mask, thereby forming gate lines 102 and storage capacitance lines 113 out of the metal thin film 102.
In this method, even if the gate lines 102 are subsequently formed over, and somewhat misaligned with, the data lines 105 and drain electrodes 109 that were formed first, the gate lines 102 still can overlap both the data lines 105 and the drain electrodes 109 in sufficiently large areas. As a result, the unwanted variation in gate-drain capacitance Cgd is suppressible.
In the structure illustrated in FIGS. 46A and 46B, however, the i-semiconductor layer 106 exists in thin stripes under the gate lines 102 and crosses all the data lines 105. Accordingly, when a scan signal (or select signal) is input to one of the gate lines 102 to turn the TFT 110 ON, part of the semiconductor layer 106 located between the drain electrode 109 and the data line 105 on the left-hand side of the drain electrode 109 naturally serves as a channel region for the TFT 110. In addition, another part of the semiconductor layer 106 located between the drain electrode 109 and the data line 105 on the right-hand side of the drain electrode 109 also serves as a channel region for a parasitic transistor unintentionally. In that case, crosstalk should occur between two horizontally adjacent pixels. As a result, the display contrast of an active-matrix-addressed LCD with such a structure, which should be high enough otherwise, decreases disadvantageously.
To solve this problem, an active matrix substrate with the structure shown in FIG. 47 was proposed as disclosed in Japanese Laid-Open Publication No. 61-108171. The active matrix substrate shown in FIG. 47 has basically the same structure as the counterpart shown in FIGS. 45A and 45B. The structure shown in FIG. 47 is different from that shown in FIGS. 45A and 45B in that the gate lines 102 have no branches (i.e., gate electrodes) but that the gate lines 102 themselves serve as gate electrodes in thin stripes. Also, in the structure shown in FIG. 47, the drain electrode 109 extends parallel to the data lines 105. In such a structure, even if the data lines 105 and drain electrode 109 are somewhat misaligned with the gate electrode (i.e., part of the gate line 102), the TFT 110 still can operate properly and the overlap area between the drain electrode 109 and gate line 102 does not change. Consequently, the variation in capacitance Cgd is suppressible.
The structure shown in FIG. 47 can increase the alignment margin up to about 10-20 μm. However, most of the exposure systems currently used for making active matrix substrates realize an alignment accuracy of less than ±1 μm. For that reason, the structure shown in FIG. 47 is rarely used now. Instead, the structure shown in FIGS. 45A and 45B is actually adopted much more often to increase the aperture ratio and to make the layout more easily modifiable when failures are found.
In another known type of structure (see Japanese Laid-Open Publication No. 63-279228), pixel electrodes are formed in a layer different from the layer where data lines belong so that the pixel electrodes, formed on an interlevel dielectric film, overlap the data lines. In such a structure, no horizontal gap is needed between the pixel electrodes and data lines because the pixel electrodes are included in a layer located over the layer where the data lines belong. As a result, the pixel electrodes can have their aperture ratio increased and an LCD including such a substrate can have its power dissipation reduced.
Recently, to reduce the weight of electronic units, LCDs fabricated on a plastic substrate, lighter in weight than a glass substrate, are sometimes modeled.
However, the sizes of a plastic substrate are changeable considerably during a fabrication process. Also, any size of a plastic substrate is changeable differently depending on a particular combination of process conditions. So an LCD on a plastic substrate currently operates too much inconsistently to put it to actual use.
A rate at which a plastic substrate changes its size (i.e., expands or shrinks) horizontally to its principal surface (which will be herein referred to as a “substrate expandability”) heavily depends on the process temperature or the amount of water absorbed into the plastic substrate. For example, the temperature-dependent expandability of a glass substrate is 3 to 5 ppm/° C., while that of a plastic substrate is as much as 50 to 100 ppm/° C. Also, a plastic substrate is expandable at as high a rate as 3000 ppm when absorbs water.
The substrate expandability reaching 3000 ppm is the maximum value in all the process steps of the fabrication process thereof. To estimate the mask misalignment actually observable in a photolithographic process, the present inventor modeled TFTs on a plastic substrate and measured how much the substrate was expandable or shrinkable in the interval between two photolithographic process steps that were performed under mutually different combinations of conditions. As a result, I found that the substrate was expandable or shrinkable between the two photolithographic process steps requiring mask alignment at about 500 to 1000 ppm.
If a plastic substrate with a diagonal size of 5 inches is expandable or shrinkable at that high rate, then the size of the substrate is changeable by 64 to 128 μm. And when the substrate size is changeable in such a wide range, no TFTs made by any known method of making an active matrix substrate are operable properly.
I estimated alignment margins allowable by the known structure shown in FIG. 47. FIG. 48 illustrates how an active matrix substrate with the basic structure shown in FIG. 47 should be laid out where an alignment margin, substantially equal to the line width of the data lines 105, is allowed for the substrate. Using this layout, I carried out a computer simulation to obtain substrate expandability that an active matrix substrate with the known structure shown in FIG. 47 and a diagonal size of 5 inches can cope with. The results are as follows:
TABLE 1Pixel pitch (μm)Alignment margin (μm)Expandability (ppm)3502437830019299250142202009142where the exposure system is supposed to have an alignment accuracy of ±0 μm. As shown in Table 1, an active matrix substrate including pixels with a pixel pitch of 250 μm, for example, allows an alignment margin of only ±14 μm or less. An active matrix substrate allowing such a narrow alignment margin can barely cope with a substrate expandability of 220 ppm or less.
As can be seen from the foregoing description, none of the known structures allows for preparing an active matrix substrate using a plastic substrate. So there has been no other choice than using a glass substrate with low shock resistance and of a hardly reducible weight for an active matrix substrate.